View ADP3342JRMZ-REEL7_5769335.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

rev. c information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ?2004 analog devices, inc. all rights reserved. adp3342 ultralow, i q , anycap low dropout regulator features accuracy over line and load: 4.0% @ 25 c, 5% over temperature ultralow dropout voltage: 190 mv (typ) @ 300 ma requires only c o = 1.0 f for stability anycap architecture stable with any type of capacitor (including mlcc) current and thermal limiting low shutdown current: < 2 a 1.7 v < v in < 6 v 2.8 v < vcc < 6 v v out = 1.2 v 5% ?0 c to +100 c ambient temperature range ultrasmall thermally enhanced 8-lead msop package applications notebook pcs desktop pcs functional block diagram general description the adp3342 is a unique member of the adp330x family of precision low dropout anycap voltage regulators. the adp3342 operates with an input voltage range of 1.7 v to 6 v and delivers a continuous load current up to 300 ma. in order to support the ability to regulate from such a low input voltage, the power rail to the ic, vcc, has been split off from the main power rail, v in , from which the output is powered. the adp3342 stands out from the conventional ldos with the lowest thermal resistance of any msop-8 package and an enhanced process that enables it to offer performance advan- tages beyond its competition. its patented design requires only a 1.0 f output capacitor for stability. this device is insensitive to output capacitor equivalent series resistance (esr) and is stable with any good quality capacitor, including ceramic (mlcc) types for space-restricted applications. the dropout voltage of the adp3342 is only 190 mv (typical) at 300 ma. this device also includes a safety current limit, thermal overload protection, and a shutdown control pin. + vcc in sd out pwrgd gnd adp3342 + on off 1 f v in 1.8v 1 f v out 1.2v 3.3v figure 1. typical application circuit thermal protection cc in adp3342 out gnd q1 g m band gap + ref driver vcc pwrgd sd
rev. c ? adp3342?pecifications 1, 2 (vcc = 3.0 v, v in = 1.8 v, c in = c out = 1 f, t a = 0 c to 100 c, and t a = ?0 c to +100 c, unless otherwise noted.) parameter symbol conditions min typ max unit output voltage accuracy v out vcc = 2.8 v to 6 v, v in = 1.7 v to 6 v ?.0 +4.0 % i l = 0.1 ma to 300 ma t a = 25 c vcc = 2.8 v to 6 v, v in = 1.7 v to 6 v ?.0 +5.0 % i l = 0.1 ma to 300 ma t a = ?0 c to +100 c line regulation vcc = 2.8 v to 6 v, v in = 1.7 v to 6 v 0.04 mv/v t a = 25 c load regulation i l = 0.1 ma to 300 ma 0.12 mv/ma t a = 25 c dropout voltage v drop v out = 98% of v outnom i l = 300 ma 190 450 mv i l = 200 ma 125 mv i l = 100 ma 70 mv current limiting i lim vcc = 3 v, v in = 1.8 v 450 ma output noise v noise f = 10 hz?00 khz, c l = 1 m f60 m v rms i l = 300 ma operating currents ground current in regulation i gnd i l = 300 ma, t a = ?0 c to +100 c 3.0 8.5 ma i l = 300 ma, t a = 0 c to 100 c 3.0 6.0 ma i l = 300 ma, t a = 25 c 3.0 4.0 ma i l = 200 ma 2.0 ma i l = 0.1 ma 100 175 m a vcc current in regulation i vcc i l = 300 ma 100 170 m a ground current in shutdown i gndsd sd = 0 v, vcc = 6 v, v in = 1.8 v 0.01 2 m a shutdown threshold voltage v thsd on vcc ?0.9 v off 0.6 v sd input current i sd 0 sd 6 v 1.4 7 m a output current in shutdown i osd t a = 25 c, vcc = 6 v, v in = 6 v 0.01 1 m a t a = 100 c, vcc = 6 v, v in = 6 v 0.01 2 m a pwrgd output current i pwrgdl v pwrgd = 1.2 v, vcc = 3.0 v 0.85 1.5 ma output low voltage v pwrgdl 3 i pwrgd = 300 m a 0.4 v output high voltage v pwrgdh 3 i pwrgd = 300 m a vcc ?0.4 v on-time delay td1 4 i l = 3 ma to 300 ma, 5 300 m s c out = 1 m f to 10 m f td2 5 i l = 3 ma to 300 ma, 50 300 m s c out = 1 m f to 10 m f off-time delay td3 6 i l = 3 ma to 300 ma, 0.05 1 m s c out = 1 m f to 10 m f thermal protection shutdown temperature th prot i l = 100 ma 165 c notes 1 all limits at temperature extremes are guaranteed via correlation using standard statistical quality control (sqc) methods. 2 ambient temperature of 100 c corresponds to a junction temperature of 125 c under typical full load test conditions. 3 v pwrgdl , v pwrgdh : power good output voltages. guaranteed by design and characterization. 4 td1: delay time from v out crossing 1 v to pwrgd high. guaranteed by design. 5 td2: delay time from sd high to pwrgd high. guaranteed by design. 6 td3: delay time between sd low to pwrgd low. guaranteed by design. specifications subject to change without notice.
rev. c adp3342 e3e caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the adp3342 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. absolute maximum ratings * input supply voltage . . . . . . . . . . . . . . . . . . . C C C C ja (2-layer board) . . . . . . . . . . . . . . . . . . . . . . . . . . 205 ja (4-layer board) . . . . . . . . . . . . . . . . . . . . . . . . . . 142 jc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 C sd s dd d s
rev. c e4e adp3342etypical performance characteristics input voltage e v output voltage e v 1.7 2.7 3.7 4.7 5.7 1.17 1.18 1.19 1.20 1.21 1.22 1.23 1.24 1.25 v out = 1.2v v cc = 3v i l = 100ma i l = 300ma i l = 200ma i l = 0ma tpc 1. line regulation output voltage vs. supply voltage output load e ma ground current e ma 3.5 0 50 100 150 200 250 300 3.0 2.5 2.0 1.5 1.0 0 0.5 v in = 1.8v v cc = 3.0v tpc 4. ground current vs. load current output load e ma input/output voltage e v 0.25 0 50 100 200 250 150 300 0.20 0.15 0.10 0.05 0 tpc 7. dropout voltage vs. output current output load e ma output voltage e v 0 50 100 150 200 250 300 1.23 1.22 1.21 1.20 1.19 1.18 1.17 v in = 1.8v v cc = 3.0v tpc 2. output voltage vs. load current junction temperature e c output channel e % 1.0 0.3 e50 e25 150 0255 075 100 125 0.9 0.7 0.6 0.5 0.4 0.8 0.2 0.1 0 e0.1 e0.2 e0.3 e0.4 0 200ma 300ma tpc 5. output voltage variation vs. junction temperature temperature e c ground current @ 300ma load e ma 7.0 6.5 6.0 5.5 5.0 4.5 e40 e25 e10 5 20 35 50 65 80 0 4.0 3.5 3.0 2.5 2.0 1.5 1.0 v cc = 3.0v v in = 1.8v 95 max typ min tpc 8. ground current @ 300 ma load vs. ambient temperature input voltage e v ground current e a 120 110 100 90 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 4.4 4.8 5.2 5.6 6.0 80 70 60 50 v out = 1.2v v cc = 3v i l = 0 a tpc 3. ground current vs. supply voltage junction temperature e c ground current e ma 5.50 e40 e20 0 20 4 06080100 5.00 4.50 4.00 3.50 3.00 2.50 2.00 1.50 1.00 0.50 0 v cc = 3.0v v in = 1.8v i l = 0ma i l = 100ma i l = 200ma i l = 300ma tpc 6. ground current vs. junction temperature time e s 200 400 600 800 v out = 1.2v sd = v in r l = 4 input/output voltage e v 4 3 2 1 0 0 1000 e1 e2 5 6 tpc 9. power-up/power-down
rev. c adp3342 e5e time e s 40 80 120 160 1.32 1.22 1.12 3.00 1.80 v cc = 3v c l = 1 f r l = 4 v in e v v out e v 0 200 tpc 10. line transient response time e s 400 1200 800 1.3 1.2 1.1 200 5 v cc = 3v v in = 1.8v c l = 10 f 400 0 ma 0 1600 2000 v tpc 13. load transient response time e s 100 200 300 400 2.0 1.0 0 3.0 0 1.8 0 v cc = 3v v in = 1.8v r l = 4 sd e v output e v pwrgd e v 0 500 tpc 16. turn on delay time e s 40 80 120 160 1.32 1.22 1.12 3.00 1.80 v cc = 3v c l = 10 f r l = 4 v in e v v out e v 0 200 tpc 11. line transient response time e s 200 400 600 800 1.2 0 1.0 0.5 0 v in = 1.8v a 0 1000 v tpc 14. short circuit current time e s 6101418 2.0 1.0 0 3.0 0 1.8 0 v cc = 3v v in = 1.8v r l = 4 2 sd e v output e v pwrgd e v tpc 17. turn off delay time e s 400 1200 800 1.3 1.2 1.1 200 5 v cc = 3v v in = 1.8v c l = 1 f 400 0 ma 0 1600 2000 v tpc 12. load transient response time e s 200 600 1000 1400 2.0 1.0 0 3.0 0 1.8 0 v cc = 3v r l = 4 v in = 1.8v sd e v output e v pwrgd e v e200 1800 tpc 15. power-on/power-off response from shutdown time e s 200 600 1000 1400 2.0 1.0 0 3.0 0 v cc e v output e v v in = 1.8v sd = 3.0v r l = 4 1800 tpc 18. power-on/power-off response from v cc
rev. c e6e adp3342 time e s 200 400 600 800 1.2 0 3.0 0 1.8 0 v in = 1.8v sd = 3.0v r l = 4 v in e v output e v pwrgd e v 0 1000 tpc 19. power-on/power-off response from v in frequency e hz voltage noise spectral density e v/ hz 100 10 10 1 0.1 0.01 0.001 100 1k 10k 100k 1m c l = 10 f c l = 1 f v out = 1.2v i l = 1ma tpc 22. output noise density time e ms 5253545 3.6 3.0 400 200 0 v in = 1.8v sd = 3v 15 v cc e v ma tpc 25. current limiting from v c frequency e hz ripple rejection e db 10 100 1k 10k 100k 1m 10m e20 e30 e40 e50 e60 e70 e80 e90 v out = 1.2v c l = 1 f i l = 50 a c l = 1 f i l = 300ma c l = 10 f i l = 300ma c l = 10 f i l = 50 a tpc 20. power supply ripple rejection ambient temperature e c output voltage e v 1.25 1.23 1.21 1.19 1.17 1.15 0ma 50ma 100ma 200ma 300ma 35 55 75 95 115 135 155 175 tpc 23. thermal protection c l e f rms noise e v 70 0 10 20 30 40 50 60 50 40 20 10 0 30 300ma 0ma tpc 21. rms noise vs. c l (10 hz to 100 hz) v in e v 1.5 1.7 1.8 2.0 650 600 550 500 1.6 i cl e ma 1.9 tpc 24. current limit vs. v in
rev. c adp3342 e7e theory of operation the anycap ldo adp3342 uses a single control loop for regulation and reference functions. the output voltage is sensed by a resistive voltage divider consisting of r1 and r2. feedback is taken from this network by way of a series diode (d1) and a second resistor divider (r3 and r4) to the input of an amplifier. ptat v os noninverting wideband driver input q1 adp3342 compensation capacitor attenuation (v band ga p /v out ) r1 d1 r2 r3 r4 output ptat current (a) c load r load gnd g m vcc figure 2. control loop functional block diagram a very high gain error amplifier is used to control this loop. the amplifier is constructed in such a way that at equilibrium it pro- duces a large, temperature proportional input offset voltage that is repeatable and very well controlled. the temperature proportional offset voltage is combined with the complementary diode voltage to form a virtual band gap voltage, implicit in the network, although it never appears explicitly in the circuit. ultimately, this patented design makes it possible to control the loop with only one ampli- fier. this technique also improves the noise characteristics of the amplifier by providing more flexibility on the trade-off of noise sources that lead to a low noise design. the r1, r2 divider is chosen in the same ratio as the band gap voltage to the output voltage. although the r1, r2 resistor divider is loaded by the diode d1 and a second divider consisting of r3 and r4, the values can be chosen to produce a temperature stable output. this unique arrangement specifically corrects for the loading of the divider so that the error resulting from base cur- rent loading in conventional circuits is avoided. the patented amplifier controls a new and unique noninverting driver that drives the pass transistor, q1. the use of this special noninverting driver enables the frequency compensation to include the load capacitor in a pole splitting arrangement to achieve reduced sensitivity to the value, type, and esr of the load capacitance. most ldos place very strict requirements on the range of esr values for the output capacitor because they are difficult to stabilize due to the uncertainty of load capacitance and resis- tance. moreover, the esr value, required to keep conventional ldos stable, changes depending on load and temperature. these esr limitations make designing with ldos more difficult because of their unclear specifications and extreme variations over temperature. with the adp3342 anycap ldo, this is no longer true. it can be used with virtually any good quality capacitor, with no con- straint on the minimum esr. this innovative design allows the circuit to be stable with just a small 1 f capacitor on the out- put. additional advantages of the pole splitting scheme include superior line noise rejection and very high regulator gain, which leads to excellent line and load regulation. additional features of the circuit include current limit, thermal shutdown, and noise reduction. application information pc application?vccvid the adp3342 has been optimized for pc applications that require a 1.2 v output for powering the voltage identification rail, v ccvid . the rail from which the output draws current, the in pin, is separated from the rail that powers the ic, the vcc pin. this allows a higher efficiency design when, as recommended for imvp-3/5 applications, the vcc pin is connected to a 3.3 v supply to power the ic adequately, and the in pin is connected to a 1.8 v supply. the efficiency is nearly 60% in this case. capacitor selection as with any voltage regulator, output transient response is a func- tion of the output capacitance. the adp3342 is stable with a wide range of capacitor values, types, and esr (anycap). a capacitor as low as 1 f is all that is needed for stability; larger capacitors can be used if high output current surges are anticipated. the adp3342 is stable with extremely low esr capacitors (esr a 0), such as multilayer ceramic capacitors (mlcc) or oscon. note that the effective capacitance of some capacitor types may fall below the minimum at cold temperature. ensure that the capacitor provides more than 1 f at minimum temperature. input bypass capacitor an input bypass capacitor is not strictly required but is advis- able in any application involving long input wires or high source impedance. connecting a 1 f capacitor from in to ground reduces the circuit sd sd d
rev. c e8e adp3342 calculating junction temperature device power dissipation is calculated as follows: pvv i v i di n out load in gnd = () + C i load and i gnd are load current and ground current, and v in and v out are input and output voltages, respectively. assuming i load = 300 ma, i gnd = 4 ma, v in = 1.8 v, and v out = 1.2 v, device power dissipation is p d = () + () = 18 12 300 18 4 187 .?. . vv ma vm amw the adp3342 is capable of supplying 300 ma @ v in = 1.8 v in a typical notebook pc application. if a higher input voltage is used (such as 3.3 v), the power dissipation of the adp3342 will be limited by the thermal overload protection. assuming a 4-layer board, the junction temperature rise above ambient temperature will be approximately equal to d tmwcwc a j = =
rev. c adp3342 e9e outline dimensions 8-lead mini small outline package [msop] (rm-8) dimensions shown in millimeters 0.80 0.60 0.40 8 0 85 4 1 4.90 bsc pin 1 0.65 bsc 3.00 bsc seating plane 0.15 0.00 0.38 0.22 1.10 max 3.00 bsc coplanarity 0.10 0.23 0.08 compliant to jedec standards mo-187aa
rev. c e10e adp3342 revision history location page 11/04?data sheet changed from rev. b to rev. c. changes to ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3/03?data sheet changed from rev. a to rev. b. changes to features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 changes to figure 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 changes to specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 changes to absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 changes to pin function descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 changes to pc application
e11e
c02712e0e11/04(c) e12e

▲Up To Search▲

Price & Availability of ADP3342JRMZ-REEL7

	To Download ADP3342JRMZ-REEL7 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .